This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...

An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. Designers typically implement a ...

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...